Semiconductor structure and method for forming the same

ABSTRACT

A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.

PRIORITY CLAIM AND CROSS-REFERENCE

This application claims priority to U.S. Provisional Application Ser.No. 62/243,920, filed Oct. 20, 2015, which is herein incorporated byreference.

BACKGROUND

Devices made from semiconductor materials are used to create memorycircuits in electrical components and systems. Memory circuits are thebackbone of such devices as data and instruction sets are storedtherein. Maximizing the number of memory elements per unit area on suchcircuits minimizes their cost and thus is impetus in the designing ofsuch circuits.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 is a flow chart of a method for forming a semiconductor structureaccording to some embodiments of the present disclosure.

FIGS. 2A-2E and FIGS. 2G-2L are cross-sectional views of a semiconductorstructure at plural intermediate stages of the method for forming thesemiconductor structure in accordance with some embodiments of thepresent disclosure.

FIG. 2F is a schematic top view of the semiconductor structure of FIG.2E.

FIG. 3A is a top view of a semiconductor structure according to someembodiments of the present disclosure.

FIG. 3B is a cross-sectional view taken along line 3B-3B of FIG. 3A.

FIG. 4 is a top view of a semiconductor structure according to someembodiments of the present disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

FIG. 1 is a flow chart of a method 100 for forming a semiconductorstructure according to some embodiments of the present disclosure. FIGS.2A-2E and FIGS. 2G-2L are cross-sectional views of the semiconductorstructure 200 at plural intermediate stages of the method 100 forforming the semiconductor structure 200 in accordance with someembodiments of the present disclosure. It is understood that additionalsteps may be implemented before, during, or after the method 100, andsome of the steps described may be replaced or eliminated for otherembodiments of the method 100. The semiconductor structure 200 and themethod 100 making the same are collectively described with reference tovarious figures.

Referring to FIG. 1 and FIG. 2A, the method 100 begins at step 102 byforming at least one isolation structure 212 in a substrate 210. In someembodiments, the substrate 210 is a silicon substrate. In some otherembodiments, the substrate 210 can be made of other materials, includingsilicon, carbon, germanium, gallium, arsenic, nitrogen, aluminum,indium, and/or phosphorus. The substrate 210 may also be a bulksubstrate or have a semiconductor-on-insulator (SOI) structure.

The isolation structure 212, such as shallow trench isolation (STI) orlocal oxidation of silicon (LOCOS), may be disposed in the substrate 210to define and electrically isolate at least one active region AR. Insome embodiments, formation of an STI feature may include dry etching atrench in the substrate 210 and filling the trench with at least oneinsulating material, such as silicon oxide, silicon nitride, or siliconoxynitride. The filled trench may have a multilayer structure, such as athermal oxide liner filled with silicon nitride or silicon oxide. Insome embodiments, the STI structure may be created using a processingsequence such as: growing a pad oxide, forming a low pressure chemicalvapor deposition (LPCVD) nitride layer, patterning an STI opening usingphotoresist and masking, etching a trench in the substrate, optionallygrowing a thermal oxide trench liner to improve the trench interface,filling the trench with chemical vapor deposition (CVD) oxide, usingchemical mechanical polishing (CMP) processing to etch back andplanarize, and using a nitride stripping process to remove the siliconnitride.

In the cases wherein the substrate 210 has an semiconductor-on-insulator(SOI) structure, the trench may be deep enough to reach the buried oxidelayer, so that the subsequently formed devices are enclosed indielectric materials, and thus the leakage current is reduced.

The method 100 proceeds to step 104 by forming at least one memory celland at least one dummy feature on the substrate 210. FIGS. 2B-2Fillustrate formation of the memory cells MC and the dummy features DF.FIG. 2F is a schematic top view of the semiconductor structure 200 ofFIG. 2E.

Referring to FIG. 2B, a tunneling layer 220, a floating gate layer 230,a blocking layer 240, a control gate layer 250, a first capping layer260, and a second capping layer 270 are subsequently formed on thesubstrate 210.

The tunneling layer 220 may be an oxide layer formed by any oxidationprocess, such as wet or dry thermal oxidation or an in-situ steamgeneration (ISSG) process, in an ambient comprising H₂O, NO, or acombination thereof, or by a chemical vapor deposition (CVD) techniqueusing tetra-ethyl-ortho-silicate (TEOS) and oxygen as precursors. Thetunneling layer 220 may also include at least one high-k dielectricmaterial, such as hafnium dioxide (HfO₂), silicon nitride, siliconoxynitride, or the like. In some embodiments, the tunneling layer 220 isless than about 200 angstroms in thickness. It should be appreciated,however, that the dimensions cited in the specification are examples,and these dimensions will change with the scaling of integratedcircuits.

The floating gate layer 230, also sometimes referred to as a storagelayer, is formed on the tunneling layer 220. In some embodiments, thefloating gate layer 230 is a dielectric layer with a high trap density,which may include nitride. Charges are stored in the floating gate layer230 around traps. Alternatively, the floating gate layer 230 includes atleast one conductive material, such as polysilicon, amorphous silicon,or the like.

The blocking layer 240 may include a low-leakage dielectric material,such as HfO₂, or other dielectric materials, such as silicon oxide. Theblocking layer 240 may be formed by, for example, physical vapordeposition (PVD), atomic layer chemical vapor deposition (ALCVD),metal-organic CVD (MOCVD), or the like. The effective oxide thickness ofthe blocking layer 240 may be less than about 170 angstroms.

In some embodiments, the control gate layer 250 includes dopedpolysilicon. For example, the control gate layer 250 may be heavilydoped with phosphorus, arsenic or boron. The method for forming thecontrol gate layer 250 may include, for example, PVD. The first cappinglayer 260 is a dielectric layer and may be made of a dielectricmaterial, such as oxide, nitride, oxynitride, or combinations thereof.The second capping layer 270 is a dielectric layer and may be made ofsilicon nitride.

The blocking layer 240, the control gate layer 250, the first cappinglayer 260, and the second capping layer 270 are then patterned.Reference is made to FIG. 2C. FIG. 2C illustrates a resulting structureafter the patterning the structure shown in FIG. 2B. The blocking layers240 a, the control gate layers 250 a, the first capping layers 260 a,and the second capping layers 270 a are formed and stacked as the stackST1, and the blocking layers 240 b, the control gate layers 250 b, thefirst capping layers 260 b, and the second capping layers 270 b areformed and stacked as the stack ST2. Herein, though it is not shown, thestacks ST2 surround the stacks ST1. The stacks ST1 and ST2 arerespectively portions of memory cells and dummy features formed insubsequent processes.

Reference is made to FIG. 2D. Plural first sidewall spacers 282 areformed on sidewalls of the stacks ST1 and the stacks ST2. The firstsidewall spacers 282 may be made of nitride, silicon nitride, and/orother dielectric materials.

Reference is made to FIG. 2E. The floating gate layer 230 (referring toFIG. 2D) is patterned to form the floating gate layers 230 a and 230 b.Herein, a dry etching process may be performed. The second cappinglayers 270 a, the second capping layers 270 b, and the first sidewallspacers 282 are used as masks to prevent the control gate layers 250 aand the control gate layers 250 b from etching away.

After the patterning process, at least one memory cell MC and at leastone dummy feature DF are formed on the substrate 210. As shown in FIG.2E, each of the memory cells MC includes a stack of the floating gatelayer 230 a, the blocking layer 240 a, the control gate layer 250 a, thefirst capping layer 260 a, and the second capping layer 270 a frombottom to top. Each of the dummy features DF includes a stack of thefloating gate layer 230 b, the blocking layer 240 b, the control gatelayer 250 b, the first capping layer 260 b, and the second capping layer270 b from bottom to top.

After the formation of the memory cells MC and the dummy features DF, atleast one source region SR is formed in the substrate 210 between atleast one pair of the memory cells MC. In some embodiments, the sourceregion SR may be formed by one or more ion implantation processes.Alternatively, in some other embodiments, the source region SR may beportions of an epitaxy layer. Though it is not shown, in someembodiments, the source region SR may extend beneath edge portions ofthe floating gate layers 230 a.

Reference is made to FIG. 2E and FIG. 2F. FIG. 2F is a top view of thesemiconductor structure 200 according to some embodiments of the presentdisclosure, while FIG. 2E is the cross-sectional view taken along line2E-2E of FIG. 2F. In FIG. 2F, the isolation structures 212 are depictedas the region indicated by the dashed lines, and the memory cells MC andthe dummy features DF are depicted as hatched patterns.

The dummy features DF surround the memory cells MC. For clearillustration, herein, at least one of the dummy features DF defines acell region CR and a non-cell region NR of the substrate 210. The pluralmemory cells MC are disposed on the cell region CR for a flash memorydevice. Other non-memory devices, such as core devices, may be formed onthe non-cell region NR. In the present embodiments, the dummy featuresDF encircle the memory cells MC. To be specific, the projections of thedummy features DF on the substrate 210 form closed graphs, such asrectangles, enclosing the projections of the memory cells MC on thesubstrate 210. In some embodiments, the closed graphs may be circles,squares, or trapezoids, other than the rectangles shown in FIG. 2F.Though it is not shown, in some embodiments, the projections of thedummy features DF on the substrate 210 may not form the closed graphs,but the memory cells MC may be partially surrounded by the dummyfeatures

DF.

Herein, the memory cells MC are surrounded by two dummy features DF, oneof the dummy features DF is formed on the isolation structure 212, andthe other of the dummy features DF is formed away from the isolationstructure 212. However, the number and locations of the dummy featuresDF should not limit various embodiments of the present disclosure. Insome embodiments, the memory cells MC are surrounded by one dummyfeature DF. In some embodiments, the dummy features DF may be all formedon the isolation structure 212 or all formed away from the isolationstructure 212 and out of the active region AR.

In FIG. 2F, there are plural predetermined regions DR′ adjacent to thememory cells MC, depicted as the regions indicated by dashed lines andfilled with dotted patterned. The predetermined regions DR′ indicatespositions of plural drain regions which are to be formed in thesubsequently processes. The configuration of the common source regionsSR illustrated herein is not intended to limit various embodiments ofthe present disclosure. In some embodiments, at least one common drainregion may be disposed between at least one pair of the memory cells,and source regions are disposed respectively adjacent to the memorycells.

Referring to FIG. 2G, following ion implantation, plural second sidewallspacers 284 are formed adjacent to the first sidewall spacers 282 on thesidewalls of the memory cells MC and the dummy features DF. The secondsidewall spacers 284 may be made of oxide, the combination of oxide,nitride and oxide (ONO), and/or other dielectric materials.

Herein, the second sidewall spacers 284 on the opposite sidewalls of thedummy features DF have the same structure, while the second sidewallspacers 284 on the opposite sidewalls of the memory cells MC havedifferent structures respectively. For example, the second sidewallspacers 284 adjacent to the dummy features DF and one of the secondsidewall spacers 284 adjacent to the memory cells MC have a thickerthickness adjacent to the controlling gate layer 250 a and 250 b and athinner thickness adjacent to the floating gate layer 230 a and 230 brespectively. Comparatively, the other one of the second sidewallspacers 284 adjacent to the memory cells MC has a more uniform thicknessthan that of the second sidewall spacers 284 adjacent to the dummyfeatures DF.

In some other embodiments, though it is not depicted, the secondsidewall spacers 284 adjacent to the dummy features DF may be the sameas the second sidewall spacers 284 adjacent to the memory cells MCrespectively. Alternatively, the second sidewall spacers 284 adjacent tothe dummy features DF may have different structures from any one of thesecond sidewall spacers 284 adjacent to the memory cells MC.

Referring to FIG. 1 and FIG. 2H, the method 100 proceeds to step 106 byforming a gate electrode layer 290 on the memory cells MC and the dummyfeatures DF. Referring to FIG. 2H, the gate electrode layer 290 isformed over the substrate 210 and overlying the memory cells MC and thedummy features DF. The gate electrode layer 290 may be made ofpolysilicon. Alternatively, the gate electrode layer 290 may includedoped polysilicon, amorphous silicon, other suitable conductivematerials, or combinations thereof. The gate electrode layer 290 may beformed by CVD, plasma-enhanced chemical vapor deposition (PECVD), LPCVD,or other proper processes.

Herein, the gate electrode layer 290 includes upper portions 292, upperportions 294, recessed portions 296, and at least one recessed portion298. The upper portions 292 are disposed on the dummy features DF. Theupper portions 294 are disposed on the memory cells MC. The recessedportions 296 are disposed between the dummy features DF or/and thememory cells MC. The recessed portion 298 is disposed out of theoutermost dummy feature DF. The upper portions 292, the upper portions294, the recessed portions 296, and the recessed portion 298 may includesubstantially the same thickness. The upper surface S2 of the gateelectrode layer 290 may conform to that of the resulting structure ofFIG. 2F, such that projections of the upper portions 292 of the gateelectrode layer 290 on the substrate 210 have a profile similar to theclosed graphs of the dummy features DF shown in FIG. 2F, and the gateelectrode layer 290 may form at least one recess R1 therein.

Referring to FIG. 1 and FIG. 2I, the method 100 proceeds to step 108 byapplying a flowable material 300 on the gate electrode layer 290.

In the absence of the dummy features DF, the gate electrode layer 290 inthe non-cell region NR may be flat, and the flowable material 300applied thereon may flow away from the substrate 210 (for example, awayfrom the cell region CR), such that the flowable material 300 coated onthe gate electrode layer 290 may be too thin on the recessed portions296. The thin flowable material 300 provides little protection againstthe subsequent etching processes.

In some embodiments, the dummy features DF surrounding the memory cellsMC limit the flow of the flowable material 300. On one hand, theflowable material 300 applied on the gate electrode layer 290 is atleast partially confined in the recesses R1 by the upper portions 292.On the other hand, the configuration of the dummy features DF increasesthe contact area between the flowable material 300 and the gateelectrode layer 290, and therefore an adhesion force therebetween isenhanced and can reduce the flow rate of the flowable material 300.Therefore, the flowable material 300 is prevented from flowing away fromthe cell region CR. Through the configuration, the flowable material 300on the recessed portions 296 is thickened. For example, as shown in FIG.2I, the flowable material 300 on the recessed portions 296 has a thickerthickness T1 than a thickness T2 of the flowable material 300 on therecessed portion 298, which is out of the outermost dummy feature DF inthe non-cell region NR.

In addition, with the influence of gravity, the thickness of theflowable material 300 changes gradually based on the variation of theheights of the gate electrode layer 290. To be specific, the flowablematerial 300 may have a thickness T3 on the upper portions 292 and 294of the gate electrode layer 290, and the thickness T1 on the recessedportions 296 of the gate electrode layer 290 is thicker than thethickness T3. Due to the variation of the thickness of the flowablematerial 300, the upper surface S1 of the flowable material 300 is moreuniform than the upper surface S2 of the gate electrode layer 290. Thatis, the upper surface S1 of the semiconductor structure 200 in FIG. 2Iis more uniform than the upper surface S2 of the semiconductor structure200 in FIG. 2H.

In some embodiments, the flowable material 300 has a low viscosity in arange from 1 micron pascal-second to 300 pascal-seconds. In someembodiments, the flowable material 300 is bottom anti-reflective coating(BARC), which includes inorganic or organic material. In someembodiments, the flowable material 300 includes organic material that isphotocurable. For example, the flowable material 300 may be aphotoresist. Alternatively, in some embodiments, the flowable material300 may be other removable materials. The flowable material 300 may beformed using appropriate spin-on techniques.

Referring to FIG. 1, FIG. 2I, and FIG. 2J, the method 100 proceeds tostep 110 by removing the flowable material 300 and at least a portion ofthe gate electrode layer 290 above the memory cells MC and the dummyfeatures DF.

Herein, an etching back process is performed. The etching back processmay be performed without masking the regions between the dummy featuresDF or/and the memory cells MC. The etching back process reduces theheight of the upper surface S1 of the semiconductor structure 200, andmay stop when the top surfaces of the memory cells MC are exposed. Dueto the protection of the flowable material 300 with varying thickness,the etching back process can remove the flowable material 300, the upperportions 292, and the upper portions 294 while leaving at least portionsof the recessed portions 296 and the recessed portions 298 of the gateelectrode layer 290. Therefore, as shown in FIG. 2J, the remaining gateelectrode layer 290′ is left.

In other words, since the configuration of the dummy features DFthickens the flowable material 300 above the recessed portions 296 andmakes the upper surface of the semiconductor structure 200 become moreuniform (e. g. the surface S1 is more uniform than the surface S2), theremaining gate electrode layer 290′ may be thickened and has a uniformupper surface S3 as well.

Herein, the thickness of the remaining gate electrode layer 290′ mayrelate to etching rates of the gate electrode layer 290 and the flowablematerial 300 and a difference between the thickness T3 and the thicknessT1 of the flowable material 300. In some embodiments, the resultingupper surface S3 of the remaining gate electrode layer 290′ is adjustedbelow the top surfaces of the memory cells MC and the dummy features DF.Alternatively, though it is not shown, in some embodiments, theresulting upper surface S3 of the remaining gate electrode layer 290′may be substantially level with the upper surfaces of the memory cellsMC and the dummy features DF.

Referring to FIG. 1, FIG. 2J and FIG. 2K, the method 100 proceeds tostep 108 by patterning the remaining gate electrode layer 290′ to formword lines 290 a and an erase gate 290 b. As shown in FIG. 2K, at leastone of the word lines 290 a is formed adjacent to the floating gatelayer 230 a and the control gate layer 250 a of one of the memory cellsMC, and the erase gate 290 b is formed between at least one pair of thememory cells MC and adjacent to the floating gate layers 230 a and thecontrol gate layers 250 a of the pair of the memory cells MC. Throughthe configuration of the dummy features DF, since the remaining gateelectrode layer 290′ (referring to FIG. 2J) is thickened and has theuniform upper surface S3 (referring to FIG. 2J) as illustratedpreviously, the substrate 210 is prevented from being over-etched duringpatterning the remaining gate electrode layer 290′.

Herein, the remaining gate electrode layer 290′ adjacent to the dummyfeatures DF is not removed. In some embodiments, the remaining gateelectrode layer 290′ adjacent to the dummy features DF may be removedduring the formation of the word lines 290 a.

Referring to FIG. 1 and FIG. 2L, after the formation of the word lines290 a and the erase gate 290 b, drain regions DR may be formed in thesubstrate 210 adjacent to the memory cells MC. The drain regions DR maybe formed by one or more ion implantation processes. Alternatively, thedrain regions DR may be portions of an epitaxy layer. The drain regionsDR may diffuse and extend beneath the edge portions of the word lines290 a respectively, and are shared with the word lines of another pairof the memory cells (not shown).

The semiconductor structure 200 are formed with the plural memory cellsMC, and each of the memory cells MC can be erased, programmed, and readby applying various voltages to the various portions for said memorycell MC (i.e. the word line 290 a, the erase gate 290 b, the drainregions DR, the source region SR, and the control gate layer 250 aassociated with said memory cell MC). Herein, the operations of aselected one of the memory cells MC are briefly illustrated herein.

In some embodiments of the present disclosure, a programming operation(also referred to as a writing operation) takes place in a channelregion CR between the word line 290 a and the floating gate layer 230 aof the selected memory cell MC through efficient hot-electron injection.The word lines 290 a are also referred to as selection gates, which iscapable of turning on or off the portion of the channel region CR underthe word lines 290 a. During the programming operation of the selectedmemory cell MC, the channel region CR under the word line 290 a isturned on, a medium voltage may be applied to the source region SR togenerate the hot electrons, and control gate layer 250 a may be biasedto a high voltage. Through the configuration, electrons flow from thesource region SR into the channel region CR, then hop up from thechannel region CR and are stored in the floating gate layer 230 a.

During an erasing operation of the selected memory cell MC, an electricfield between the floating gate layer 230 a and the erasing gate 290 bare built such that electrons in the floating gate layer 230 a move tothe erasing gate 290 b. In some examples, in the operation of theselected memory cell MC, the control gate layer 250 a is either groundedor negatively biased, the erase gate 290 b is biased positively, and theword line 290 a and the drain region DR may be floating. Since acombination of the first sidewall spacer 282 and the second sidewallspacer 284 between the floating gate layer 230 a of the selected memorycell MC and the erase gate 290 b is thinner than a combination of thefirst sidewall spacer 282 and the second sidewall spacer 284 between thecontrol gate layer 250 a of the selected memory cell MC and the erasegate 290 b, charges may be erased from the floating gate layer 230 a tothe erase gate 290 b.

During a read operation, a voltage is applied on the word line 290 a ofthe selected memory cell MC to turn on the portion of the channel regionCR under the word line 290 a. If the floating gate layer 230 a of theselected memory cell MC is programmed with electrons, the portion of thechannel region CR under the floating gate layer 230 a will not conductor provide little conduction. If the floating gate layer 230 a of theselected memory cell MC is not programmed with electrons (in an erasedstate), the channel region CR under the floating gate layer 230 a willbe conductive. The conductivity of the channel region CR is sensed todetermine if the floating gate layer 230 a is programmed with electronsor not.

Herein, the memory cells MC and the dummy features DF are formed throughsubstantially the same steps, and the stack layers of the memory cellsMC may be substantially the same as that of the dummy features DF. Oneskilled in the art will realize that the teaching also applies to othersemiconductor structures.

FIG. 3A is a top view of a semiconductor structure 200 according to someembodiments of the present disclosure. FIG. 3B is a cross-sectional viewtaken along line 3B-3B of FIG. 3A. The semiconductor structure 200 ofFIGS. 3A and 3B is similar to the semiconductor structure 200 of FIG.2L, and the difference between the semiconductor structure 200 of FIGS.3A and 3B and the semiconductor structure 200 of FIG. 2L includes: thedummy feature DF is disposed on the active region AR defined by theisolation structure 212. Herein, the cell region CR has an area smallerthan that of the active region AR.

As illustrated previously, the dummy feature DF surrounds the memorycells MC, and therefore the dummy feature DF confines the flowablematerial (referring to the flowable material 300 in FIG. 2I) to stay inthe cell region CR. Through the configuration, during the formation ofthe word lines 290 a and the erase gate 290 b, the substrate 210 isprevented from being over-etched. Other details of the embodiments ofFIGS. 3A and 3B are similar to that of the embodiments of FIG. 2L, andtherefore not repeated herein.

FIG. 4 is a top view of a semiconductor structure 200 according to someembodiments of the present disclosure. The semiconductor structure 200of FIG. 4 is similar to the semiconductor structure 200 of FIG. 2L, andthe difference between the semiconductor structure 200 of FIG. 4 and thesemiconductor structure 200 of FIG. 2L includes: the dummy features DFhas at least one opening 01 connecting the cell region CR and thenon-cell region NR. Furthermore, in the FIG. 4, the dummy features DFare out of the active region AR and away from the isolation structure212. That is, the cell region CR has an area greater than that of theactive region AR.

In some embodiments, the dummy features DF partially surround the memorycells MC. Though the configuration, the substrate 210 is prevented frombeing over-etched in the patterning process (the formation of the wordline and the erase gate). Other details of the embodiments of FIG. 4 aresimilar to that of the embodiments of FIG. 2L, and therefore notrepeated herein.

In various embodiments of the present disclosure, through theconfiguration of dummy features, the flowable material is confined andprevented from flowing away from the substrate even if the flowablematerial has low viscosity, such that the substrate is prevented frombeing over-etched in the subsequent patterning process. Furthermore, insome embodiments of the present disclosure, the structure of the dummyfeature is substantially the same as the structure of the memory cell,and therefore no additional steps are taken for the forming the dummyfeature. The fabrication process of the dummy feature is well integratedwith the fabrication process of the memory cell.

According to some embodiments of the present disclosure, a semiconductorstructure includes a semiconductor substrate, at least one raised dummyfeature, at least one memory cell, and at least one word line. Theraised dummy feature is present on the semiconductor substrate, anddefines a cell region on the semiconductor substrate. The memory cell ispresent on the cell region. The word line is present adjacent to thememory cell.

According to some embodiments of the present disclosure, a semiconductorstructure includes a semiconductor substrate, at least one memory cell,at least one word line, and at least one raised dummy feature. Thesemiconductor substrate has a cell region thereon. The memory cell ispresent on the cell region. The word line is present adjacent to thememory cell. The raised dummy feature is present outside of the cellregion, in which the raised dummy feature has a dummy control gate layertherein, the memory cell has a control gate layer therein, and the dummycontrol gate layer of the raised dummy feature and the control gatelayer of the memory cell are made of substantially the same material

According to some embodiments of the present disclosure, a method forforming a semiconductor structure includes the following steps: formingat least one memory cell and at least one raised dummy featuresurrounding the memory cell on a semiconductor substrate; forming a gateelectrode layer on the memory cell and the raised dummy feature, inwhich the gate electrode layer has an upper portion on the raised dummyfeature and an inner recessed portion surrounded by the upper portion;and applying a flowable material on the gate electrode layer, in whichthe flowable material is at least partially confined by the upperportion of the gate electrode layer.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A semiconductor structure, comprising: asemiconductor substrate; at least one raised dummy feature present onthe semiconductor substrate, wherein the raised dummy feature defines acell region on the semiconductor substrate; at least one memory cellpresent on the cell region; and at least one word line present adjacentto the memory cell.
 2. The semiconductor structure of claim 1, whereinthe raised dummy feature has a dummy control gate layer therein, thememory cell has a control gate layer therein, and the dummy control gatelayer of the raised dummy feature and the control gate layer of thememory cell are made of substantially the same material.
 3. Thesemiconductor structure of claim 1, wherein the raised dummy feature hasa dummy floating gate layer therein, the memory cell has a floating gatelayer therein, and the dummy floating gate layer of the raised dummyfeature and the floating gate layer of the memory cell are made ofsubstantially the same material.
 4. The semiconductor structure of claim1, wherein the raised dummy feature has a dummy memory stack therein,the memory cell has a memory stack therein, and the dummy memory stackof the raised dummy feature and the memory stack of the memory cell aremade of substantially the same materials.
 5. The semiconductor structureof claim 1, wherein the raised dummy feature encircles the memory cell.6. The semiconductor structure of claim 1, wherein the raised dummyfeature has at least one opening communicating the cell region with anon-cell region outside of the cell region.
 7. The semiconductorstructure of claim 1, further comprising: at least one isolationstructure present in the semiconductor substrate for defining at leastone active region, wherein the memory cell is present on the activeregion, and the raised dummy feature is present outside of the activeregion.
 8. The semiconductor structure of claim 1, further comprising:at least one isolation structure present in the semiconductor substratefor defining at least one active region, wherein the memory cell ispresent on the active region, and the raised dummy feature is present onthe isolation structure.
 9. The semiconductor structure of claim 1,further comprising: at least one isolation structure present in thesemiconductor substrate for defining at least one active region, whereinthe memory cell and the raised dummy feature are present on the activeregion.
 10. A semiconductor structure, comprising: a semiconductorsubstrate having a cell region thereon; at least one memory cell presenton the cell region; at least one word line present adjacent to thememory cell; and at least one raised dummy feature present outside ofthe cell region, wherein the raised dummy feature has a dummy controlgate layer therein, the memory cell has a control gate layer therein,and the dummy control gate layer of the raised dummy feature and thecontrol gate layer of the memory cell are made of substantially the samematerial .
 11. The semiconductor structure of claim 10, wherein the cellregion are surrounded by the raised dummy feature.
 12. The semiconductorstructure of claim 10, wherein the raised dummy feature has at least oneopening communicating the cell region with a non-cell region outside ofthe cell region.
 13. A method for forming a semiconductor structure, themethod comprising: forming at least one memory cell and at least oneraised dummy feature surrounding the memory cell on a semiconductorsubstrate; forming a gate electrode layer on the memory cell and theraised dummy feature, wherein the gate electrode layer has at least oneupper portion on the raised dummy feature and at least one innerrecessed portion surrounded by the upper portion; and applying aflowable material on the gate electrode layer, wherein the flowablematerial is at least partially confined by the upper portion of the gateelectrode layer.
 14. The method of claim 13, wherein the upper portionof the gate electrode layer defines a cell region, the inner recessedportion is present in the cell region, the gate electrode layer furtherhas an outer recessed portion present outside of the cell region, andthe flowable material on the inner recessed portion has a thicknessthicker than a thickness of the flowable material on the outer recessedportion.
 15. The method of claim 13, further comprising: removing theflowable material and at least a portion of the gate electrode layer.16. The method of claim 15, further comprising: patterning the remaininggate electrode layer after the removing to form at least one word lineadjacent to the memory cell.
 17. The method of claim 13, wherein thememory cell and the raised dummy feature are formed throughsubstantially the same step.
 18. The method of claim 13, furthercomprising: forming at least one isolation structure in thesemiconductor substrate for defining at least one active region, whereinthe forming the memory cell and the raised dummy feature comprises:forming the memory cell on the active region and forming the raiseddummy feature outside of the active region.
 19. The method of claim 13,further comprising: forming at least one isolation structure in thesemiconductor substrate for defining at least one active region, whereinthe forming the memory cell and the raised dummy feature comprises:forming the memory cell on the active region and forming the raiseddummy feature on the isolation structure.
 20. The method of claim 13,further comprising: forming at least one isolation structure in thesemiconductor substrate for defining at least one active region, whereinthe forming the memory cell and the raised dummy feature comprises:forming the memory cell and the raised dummy feature on the activeregion.